This invention relates in general to the field of integrated circuits and, more particularly, to a method of forming poly-silicide conductors for use in such integrated circuits.
Continuous improvement in photolithographic processing capabilities allows use of smaller minimum dimensions for forming the elements of integrated circuits. The smaller dimensions tend to increase the resistances of conductors and of contacts to the conductors. One commonly used way to compensate for the smaller dimensions and the higher resistances is to use refractory metal silicide technology to form low-resistance conductors and low-resistance contacts to the conductor. Silicides include, for example, tungsten disilicide (WSi.sub.2) and titanium disilicide (TiSi.sub.2). In addition to tungsten and titanium, disilicides are formed from refractory metals such as cobalt, tantalum, molybdenum, platinum and combinations of all such metals. Processes used in forming silicided conductors are described, for example, in U.S. Pat. Nos. 5,173,450; 5,043,300; 4,931,411; 4,894,693; 4,814,854; 4,811,078; 4,811,076; 4,784,973; 4,690,730; 4,686,000; 4,619,038; 4,609,568; 4,561,907; and 4,460,435. Interestingly, U.S. Pat. No. 4,460,435, at column 3, lines 25-30 states that siliciding after etch is the preferred method. Processes are also described, for example, in the following publications: Shih-Chang Chen, et al., "Formation of Titanium Nitride/Titanium Silicide by High Pressure Nitridation in Titanium/Silicon", Japanese Journal of Applied Physics, vol. 30, No. 11A Nov. 1991, pp. 2673-2678; and Tohru Hara, et al., "Formation of Titanium Nitride Layers By the Nitridation of Titanium In High-pressure Ammonium Ambient", Applied Physics Letters, vol. 57, No. 16, Oct. 1990, pp. 1660-1662.
In known prior-art construction processes for integrated circuits, a doped polysilicon layer is formed followed by deposit of a refractory metal layer. The doped polysilicon layer and the refractory metal layer are then etched to form conductors. After the etching step, the doped polysilicon layer and the refractory metal layer are subjected to an annealing process step to form poly-silicide conductors. The prior-art process sequence allows siliciding both the conductors and the source/drain areas simultaneously.
However, certain types of integrated circuits do not require siliciding of the source/drain areas. One such type of integrated circuit is an EPROM (Electrically-Programmable, Read-Only Memory). In the memory-array part of an EPROM, the silicided polysilicon conductor forms the control gates of the memory transistor cells and the wordlines connecting those control gates to the wordline decoder. U.S. Pat. No. 4,281,397 issued Jul. 8, 1981 to Neal et al. entitled "Virtual-Ground MOS EPROM or ROM Matrix" is one example of that type of EPROM, although that patent does not describe siliciding steps, which are described in the previously-cited references.
One of the problems with use of the prior-art sequence is that EPROMs made by etching wordlines/control gates prior to anneal have memory transistor cells with a wide lot-to-lot distribution of threshold voltages Vt. While the reason for the wide distribution is not entirely understood, it is known that polysilicon conductors that are etched prior to annealing with tungsten silicide have notched, or ragged, edges. Past efforts to alter the tungsten siliciding process to minimize notching and/or tungsten crystal formation have not been successful. It is probable that the wide distribution of threshold voltages Vt results from blocked source/drain implants caused by notches and/or tungsten crystal formation on the control-gate conductors that mask such implants. A narrow range of threshold voltages is desirable because, for example, the narrow range minimizes the number of errors in data read from EPROM memory transistor cells.
There is a need for a refractory metal-silicide process that is able to produce transistors with a narrow lot-to-lot range of threshold voltages.